Semiconductor ICs typically are fabricated by successively forming patterned layers on a top major surface of a semiconductor wafer body, typically silicon. Each of the layers typically is composed of a metal, insulator, or semiconductor material that has been patterned by a lithographic masking and etching technique suitable for the material. Each lithographic step defines a device level. During the fabrication in this way of ICs containing MOS or bipolar transistor devices, or both, a set of fiducial alignment marks known as registration marks are used. Each such mark has a registration feature. A set of at least three such marks is required per wafer. Each such mark, typically having the shape of a cross when viewed from above, is formed on the surface of the wafer in a dedicated registration mark area thereof. The position of the feature of a registration mark is defined in electron beam lithography as the centroid of the mark, and in other lithographies it is defined as either the centroid or an edge of the mark. The features of these registration marks are then used for aligning the wafer with respect to the lithographic writing tool being used--e.g., optical lithography or electron-beam-IC transistor devices--i.e., the device features located in dedicated device areas--are aligned with respect to the registration marks and hence with respect to one another as desired.
Inherent in every alignment of the position of a device feature with respect to a set of registration marks is an important, non-negligible alignment error, say .+-.e. That is, the distance between a device feature and the relevant feature of the registration mark on a pre-defined level can vary by as much as .+-.e, where e represents a standard deviation, owing to unavoidable imperfections and uncontrollable random variations in the lithographic technique being used. Moreover, in cases where it is necessary to fabricate two different device levels using the same set of registration marks from an earlier level for both device levels, the standard deviation of the total alignment error in the position of one of the features with respect to the other is equal to e.sqroot.2, i.e., an error deviation equal to almost one-and-one-half times the alignment deviation of a signal level. If each level is aligned to registration marks at different levels, the alignment can become progressively worse.
In the fabrication of MOS transistors, for example, a double misalignment problem associated with the respective features of the fabricated field oxide layer and the later fabricated polysilicon gate electrode layer arises if the same earlier set of registration marks is used for aligning both the field oxide and the gate electrode.
In the prior art of optical lithography, the double misalignment problem has been avoided by lithographing the registration marks in the field oxide layer simultaneously while lithographing the field oxide edges of devices being fabricated in the device area; and these registration marks in the field oxide layer are then used for aligning the polysilicon gate electrodes. In this way, since both the registration marks and device feature are on the same lithographic level, there is no misalignment between the edges of the field oxide layer located in the device areas relative to those located in the registration mark area. Subsequent alignment of the polysilicon gate electrode results in only a single alignment error .+-.e, and not a double alignment error e.sqroot.2, between the field oxide edges and the polysilicon gate electrode edges located in the device areas. However, when using lithographic techniques other than optical lithography, such as direct electron-beam-writing lithography--as for the purpose of achieving higher resolutions, for example, 0.3 micrometer feature sizes or less in the gate level--the edge of field oxide, being contiguous with the semiconductor, do not always supply sufficient contrast, with respect to the substrate, to enable detection by the beam of the position of the oxide edge with desired precision. In particular, the edge of the field oxide, especially in the case of thin field oxide, are not accurately determinable by observing the pattern of backscattering, for example, of the electron beam in neighborhoods of these edges. Hence, such a field oxide edge cannot always serve as the desirable precise registration mark, i.e., with the virtually zero misalignment. Thus, in prior art, a lithographic level has been defined solely for the purpose of alignment. Metal or metal silicide registration marks have been used in non-optical lithographies, but at the penalty of double misalignment.